As digital design engineer, this position will be responsible for developing advanced CMOS image sensor circuits and technologies and the design of digital timing and control logic and signal processing logic for CMOS image systems on-chip.
Candidate will perform chip physical design including place & route, STA, floor-planning, formal verification and physical verification.
- Static timing analysis (STA), floor-planning, place & route (P&R), LVS, DRC, antenna, chip finishing and SoC-package co-simulation
- Defining and developing verification methodology, in accordance with project requirements,
- Participate in system level architectural design of image systems on-chip
- Work closely with analog/mixed-signal designers and software/firmware designers during chip development
The candidates will also plan, organize, execute, and thoroughly document complex mixed-signal circuit designs. Assist in developing technical solutions to customer specifications, determining the limits of new technology, and inventing novel intellectual property.
Education / Experience Requirements
- MSEE or equivalent
- Minimum 2 years of experience in ASIC physical design
- Experience in RTL design and verification of ICs is a plus
- Strong background in Cadence design tools is required
- Working experience in a related CMOS image sensor field is highly desirable, with an emphasis in low-power and high-speed designs
- Able to make system level judgment and associated trade-offs
- Knowledge of entire ASIC design methodology
- Good communication skills
- Able to work in a team environment
Interested candidates please submit updated CV to jobs firstname.lastname@example.org with the following subject: "Job application > DDE back-end specialists".