Unlike CMOS Image Sensors, Vision Systems on-chip (VSoC) are not only conceived for capturing images, but for processing in real-time such images according to an given algorithm programmed by the user and for prompting decisions based on the outcome from such image-processing.
Why choosing VSoC technology?
We could agree that today the cost of integrating processing capability into a digital camera is small. However the prevalent standard solution consisting of digital camera + frame-grabber + PC is still expensive due to the cost of image communication, especially in high-speed applications.
In VSoC image capture and processing are placed in the same SoC, therefore the need for bandwidth in image communication is drastically reduced as only selected pieces of information (features, not full-images) are downloaded or in some cases only decisions are prompted.As image sensing and processing co-exists in VSoC, it is very easy to imagine networks of VSoC cooperating to solve complex image-processing tasks.
Their inherent scalability allows joining the efforts of as many VSoC as needed, working as elements of a larger processor, to solve practically many applications.
How is an AnaFocus VSoC?
One could think that obvious way of building a VSoC is putting together a CMOS Image Sensor, a microprocessor, and some memory.
Even when previous statement is correct, very small amount of real-world applications can be solved with such architecture. The reason is in the parallel nature of image-processing.
Solving complex image-processing tasks in real-time requires enormous amounts of power processing and memory. Both items (large processing power and large memory) are “natural enemies” of system on-chip (SoC) solutions.
During +20 years AnaFocus founders conceived and developed a patent-protected architecture for performing complex and efficient image-processing in a SoC. The key concept of such architecture is parallel and multi-layer image processing.
Conceptually speaking the foundation of this processing architecture is simple: divide image-processing in many elementary processing blocks and make them work together; this way you will save big amount of processing power and image-memory compared to the standard "sensor + CPU" paradigm.
AnaFocus architecture also exploits the concept of analog image-processing.
After many years of research and numerous chips we discovered that certain image-processing operations can be implemented in analog with good accuracy and outstanding power & area efficiency. Such operators are applied directly to the analog images from the pixel array, before digitalization. Such analog processing blocks can be physically place right in the pixel array or in the shape of column-wise analog processors that operate as the image are row-by-row readout.
The previous concepts arranged in the proper architecture results in ultra-efficient VSoC architectures rivaling in performance with sophisticated and expensive multi-chip smart cameras while keeping the size and price advantage of single-chip.
How is a VSoC designed?
Creating a VSoC is a complex task involving image sensor and SoC design, software-hardware co-design and real-time image-processing.AnaFocus owns a proprietary and silicon-proven methodology for mapping a vision application (this is, an application involving image capture, image processing, and data communication) into a high-performance and cost-effective SoC.
Such methodology has been successfully applied to the development of innovative and powerful VSoC for top-tier companies who today enjoy from the market advantage provided by the availability of such exclusive and differentiated device.